A Digital to Analog Converter (DAC) is a circuit that converts digital measures of signal amplitude in discrete steps, into a continuous analog electrical equivalent of the signal to be reproduced. The amplitude is a digital number (for example, a 16 bit word) and the steps occur based on the sampling rate (for example, 44,100 times per second). This process can be seen as an approximation of mathematical integration, wherein tops of bars having fixed width and discrete height (digital amplitudes at a fixed sample rate) are used to approximate an analog curve or signal. In such a system, the number of discrete heights defines the DAC's resolution, and the width of each bar is determined by the sampling rate. The goal of the DAC is to adjust the top of each discrete bar to coincide with the level specified by the signal. Some techniques used to accomplish this include; Delta Sigma, Ladder, and the Most Significant Bit (MSB) Sign Magnitude Ladder, and each has its own limitations and post filtering requirements.
In the Delta Sigma DACs (single bit), each bar is raised to the appropriate level by selecting from evenly spaced, discrete intervals. For example, the maximum bar height could be segmented into 64 pieces for a 64 times oversampling system. By stacking or summing the discrete and identical increments, an approximation of each analog signal amplitude at a given sample is approximated. By tracking the error and by alternately exceeding or underrepresenting the analog signal over a large number of samples, good accuracy can be achieved, but only with appropriate post filtering and curve shaping techniques.
In a Ladder DAC, the height of each sample bar is established by summing together a plurality of discrete increments, but the DAC has several distinct height increments to choose from. By summing together an appropriate number of varied discrete height blocks, the overall height of a sample can be represented very accurately without post filtering. However, the accuracy is a function of the cumulative error of each of the discrete stacked increments that are summed.
In MSB Sign Magnitude Ladder DAC, operation is similar to the Ladder DAC method, however all bars are essentially prefilled to a height that is centered upon the expected range of the represented. Thereafter, the DAC sums together an appropriate number of varied discrete height blocks, and then either adds or subtracts from the starting centered bar height. In this way, a fewer number of segments must be added together, thus reducing the cumulative error when representing magnitudes near the centered value.
The digital input of a DAC may encode to either of a corresponding voltage, current, or charge signal. Current encoding DACs constructed in CMOS or bipolar technologies (including III-V and HBT) offer the benefit of relatively fast switching speeds, owing to the fact that the CMOS and bipolar junction transistors are inherently current-mode devices. The current encoding DAC, otherwise known as current-steering DACs, include an array of current cells, scaled (or weighted) in a binary fashion. For example, an N-bit current steering DAC comprises N current cells, each carrying current of I, 2*I, 4*I, 8*I, . . . , 2^(N−1)*I, respectively. While current encoding DACs offer the benefit of relatively fast switching speeds, several limitations and design constraints exist.
In high resolution DAC designs, there exists a large ratio between the current magnitudes of the LSB and MSB cells. In an N-bit DAC, the MSB current cell array sinks 2N-1 times the LSB current. For example, where the cell switches the current between I and 0, a conventional current steering cell may be established as depicted in FIG. 1. The difference in currents is the effective current, I. For the LSB cell, this current is ILSB, while for the MSB of an N-bit DAC, the magnitude of this current is 2N-1 ILSB.
This creates a significant difference in the response times of the LSB cell ( LSB) and the MSB cell ( MSB), resulting in mismatch in switching time instants, as depicted in FIG. 2. Such cell by-cell timing delays result in the formation of output glitches that can limit the speed of operation, especially in gigahertz DACs. This creates a designer's paradox that may be referred to as the Resolution-Bandwidth trade-off.
Some older methods to improve switching speeds included adopting segmentation of the current cells, such that the highest magnitude of the MSB current was made comparable to that of the LSB cell. Such high degrees of segmentation help alleviate timing mismatch problem at the penalty of increased occupied chip footprint and increased capacitance. A large chip area results in being sensitive to process variations and IR drops that affect the matching between the current cells, both temporally and spatially. Consequently, the limitations encountered by the Resolution-Bandwidth trade-off still come into play when such prior art solution are employed.
Other methods attempt to improve the dynamic performance of the DAC by the use of return-to-zero and random return-to-zero structures. However, in such prior art structures and methods the realized performance is still limited by the intrinsic switching speeds of the current cells. While the switching speeds have been shown to improve by the use of appropriate gate drives and switching loads, design flexibility is still substantially constrained.
Therefore, there exists a need in the art for a high-speed low-latency high-resolution digital to analog converter that reduces the impact of existing Resolution-Bandwidth design limitations.